Systolic Neural Accelerator on FPGA

Runs a 256-neuron subcircuit of the FlyWire FAFB v783 connectome on a Basys 3 board, closing the loop around a virtual fly that eats when sugar neurons reach the proboscis motor neurons and jumps when looming detectors reach the giant fibre. Weights are sign of transmitter times min(127, twice the synapse count) over 2,265 synapses, with no per-synapse tuning. Post-route at 100 MHz the 4x4 systolic array takes 28,937 cycles per update against 65,800 for a serial baseline. The ablation arm: over 40 trials the circuit eats 35 and escapes 39; removing all synapses gives 0 and 29.

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#fpga#systemverilog#systolic-array#uvm#ablation-control#flywire